This document aggregates precise reference data from the official datasheet and complements it with practical findings from Field Application Engineers (FAE). Analysis of transient processes, static on-state resistance, and thermal balance allows for the design of a reliable power stage with a predictable lifetime.
1 — Description and Application of FGHL25T120RWD (Background)
Key Features and Package Type
Point: COPACK (Co-Package) technology integrates a Trench Field Stop IGBT die and a fast soft-recovery diode (FRD) on a single substrate within a standard discrete TO-247-3L package form factor.
Evidence: This design reduces parasitic lead inductance and optimizes the thermal balance. The integrated diode protects the transistor from reverse currents when operating with inductive loads.
Explanation: In real-world design, this significantly saves PCB area, simplifies heatsink calculations, and reduces the requirements for snubber damping circuits.
Where to Find Packaging and Pinout in the Datasheet
Point: Package drawings and pinouts are placed in the final section of the specification ("Package Dimensions" and "Pin Configuration").
Evidence: The drawings specify precise tolerances for lead thickness, plastic capsule dimensions, and the location of the M3 screw mounting hole.
Explanation: Ignoring mechanical tolerances can lead to mechanical stress on the transistor leads when rigidly fixed to the heatsink, which, during thermal cycling, can trigger microcracks in the solder joints.
2 — Key Static Electrical Parameters (Data Analysis)
Absolute Maximum Ratings and Nominal Values
Absolute maximum ratings define the boundaries of the Safe Operating Area (SOA). Exceeding these values leads to avalanche breakdown of the structure or thermal destruction of the die.
| Parameter (Symbol) | Test Conditions | Nominal (Typ.) | Maximum Limit |
|---|---|---|---|
| Collector-Emitter Voltage (V_CES) | Tj = 25 °C, V_GE = 0 V | — | 1200 V |
| Continuous Collector Current (I_C) | Tc = 100 °C | 25 A | 50 A (@ Tc=25°C) |
| Saturation Voltage (V_CE(sat)) | I_C = 25 A, V_GE = 15 V, Tj = 25 °C | 1.8 V | 2.4 V |
| Gate-Emitter Threshold Voltage (V_GE(th)) | I_C = 25 mA, V_CE = V_GE | 5.8 V | 7.4 V |
Practical Margins in Design
Point: When designing power supplies, it is important to consider the positive temperature coefficient of the saturation voltage V_CE(sat).
Evidence: As the junction temperature Tj increases from 25°C to 175°C, the typical V_CE(sat) value increases from 1.8 V to 2.2 V.
Explanation: This property prevents localized overheating of dies when devices are connected in parallel; however, it requires the thermal calculation to account for the worst-case static losses at the maximum operating temperature.
3 — Dynamic and Pulse Characteristics (Data Analysis)
Switching Time Parameters
Point: Rise time (tr), fall time (tf), and turn-on/off delay times (td(on/off)) determine dynamic power losses during switching at high frequencies (up to 40 kHz).
Evidence: According to the specification, when switching an inductive load with a gate resistance R_G = 10 Ohm, the current fall time tf is about 15-25 ns.
Explanation: Knowing the exact fall time allows for calculating the turn-off loss energy (Eoff) and correctly selecting the "Dead-Time" in half-bridge configurations to prevent shoot-through currents.
Reverse Recovery Characteristics and dv/dt / di/dt Limits
Point: The recovery speed of the co-packaged diode (trr, Qrr) affects the level of electromagnetic interference (EMI) and overvoltages at the turn-off transient.
Evidence: High di/dt values cause short-term inductive voltage spikes across layout parasitic inductances, which can exceed V_CES.
Explanation: Using snubber capacitors of 10-100 nF in close proximity to the module's power pins allows for damping these peaks and protecting the structure from overvoltage.
4 — How to Read the FGHL25T120RWD Datasheet: A Step-by-Step Guide (Method/Guide)
"First Things First" Quick Check
When quickly evaluating the applicability of a transistor in your project, follow a strict algorithm:
- Blocking Voltage Check: Ensure that the peak voltage on the DC-link bus, taking into account transient processes, does not exceed 80% of V_CES (i.e., no more than 960 V).
- SOA (Safe Operating Area) Curve Analysis: The operating point during switching must not exceed the limits of the SOA curve at the maximum pulse duration.
- Thermal Resistance Evaluation: The Rth(j-c) (junction-to-case) value must ensure sufficient heat dissipation under the chosen cooling method.
How to Match Datasheet Parameters with Circuit Requirements
Point: The selection of the gate driver must be based on the total gate charge Q_g.
Evidence: For FGHL25T120RWD, the gate charge is approximately 120 nC under a control voltage of -5 V to +15 V.
Explanation: The driver must provide sufficient peak output current (I_peak = dQ/dt) to charge/discharge this capacitance within the required time, preventing edge degradation and die overheating.
5 — Examples of Calculations and Integration into a Real Circuit (Case Study)
Thermal Calculation and Selection of Thermal Interface Solutions
The calculation of the steady-state junction temperature (Tj) is performed using the formula:
Tj = Tc + P_total * Rth(j-c)
Where P_total is the total losses (static + dynamic), and Rth(j-c) for this device is approximately 0.45 °C/W. With total losses of 100 W and a case temperature (Tc) of 80 °C, the junction temperature will be:
Tj = 80°C + 100 W * 0.45 °C/W = 125 °C
This value is well within the allowable limit of Tj_max = 175 °C, providing a necessary safety margin of 50 °C.
On-Board Testing: Test Suite and Key Test Points
Point: During the prototype commissioning stage, instrumental monitoring of signals directly at the IGBT terminals is mandatory.
Evidence: A dual-channel oscilloscope with a bandwidth of at least 200 MHz is used to monitor gate voltage V_GE and collector current I_C.
Explanation: Special attention is paid to ensuring the absence of oscillations (ringing) on the gate, which can cause spurious turn-on of the transistor due to the Miller effect.
6 — Practical Summary of Electrical Characteristics and Selection Checklist (Action)
Brief Checklist of Key Parameters
- V_CES: 1200 V — guarantees operation in 380/400 V three-phase grids.
- I_C: 25 A DC current (Tc = 100 °C) — optimal for motors up to 5.5 kW.
- V_CE(sat): 1.8 V — low conduction losses in the 1200 V class.
- Tj_max: 175 °C — increased temperature resource of the semiconductor structure.
Recommendations for Safety, Verification, and Reliability
Point: To protect against short circuits in the load, the control circuit must support the desaturation (DESAT) function.
Evidence: The module is capable of withstanding short-circuit current for a duration t_sc of no more than 10 µs at V_GE = 15 V.
Explanation: The gate driver must instantly detect the rise of V_CE voltage above the allowable threshold during a short circuit and perform a soft turn-off to prevent destruction of the structure by self-induction currents.
Conclusion (Summary)
- FGHL25T120RWD is a balanced solution for high-voltage power electronics, requiring precise design of the gate driver and snubber circuits.
- The use of COPACK technology minimizes parasitic circuit parameters and optimizes the heat dissipation of the device.
- Implementation of short-circuit protection (DESAT) and maintaining a temperature margin of at least 30-40 °C guarantees the longevity of the converter's power stage in industrial environments.
Frequently Asked Questions (FAQ)
What are the main advantages of the TO-247 COPACK package for FGHL25T120RWD?
The TO-247 COPACK package integrates the IGBT die and a fast-recovery diode (FRD) into a single discrete package. This minimizes parasitic lead inductance, simplifies PCB layout, and significantly reduces the overall footprint of the power stage while maintaining high heat dissipation potential.
What is the significance of the VCE(sat) parameter when designing a heatsink?
The collector-emitter saturation voltage VCE(sat) directly determines the static conduction losses (Pconduction = VCE(sat) * IC). The lower this value at operating temperature (typically 1.8 V at Tj = 175°C), the less heat is generated on the die, allowing for the optimization of the heatsink dimensions.
How to minimize the impact of high dv/dt and di/dt values during switching?
To minimize the destructive effects of steep dv/dt and di/dt edges, it is recommended to use external gate resistors (RG) of optimal value to slow down switching, install RC snubber circuits in parallel with the power paths, and design the PCB layout with minimum ground loop inductance.
Why measure the short-circuit withstand time?
This parameter defines the time interval (typically up to 10 µs) during which the device can withstand a direct short-circuit current at full supply voltage. Measuring this value is critical for configuring the response time of gate driver protection systems (e.g., DESAT desaturation detection circuits).
